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74ALVC162827 Low Voltage 20-Bit Buffer/Line Driver with 3.6V Tolerant Inputs and Outputs and 26 Series Resistors in the Outputs
November 2001 Revised November 2001
74ALVC162827 Low Voltage 20-Bit Buffer/Line Driver with 3.6V Tolerant Inputs and Outputs and 26 Series Resistors in the Outputs
General Description
The ALVC162827 contains twenty non-inverting buffers with 3-STATE outputs to be employed as a memory and address driver, clock driver, or bus oriented transmitter/ receiver. The device is byte controlled. Each byte has NOR output enables for maximum control flexibility. The 74ALVC162827 is designed for low voltage (1.65V to 3.6V) VCC applications with I/O capability up to 3.6V. The ALVC162827 is also designed with 26 resistors in the outputs. The 74ALVC162827 is fabricated with an advanced CMOS technology to achieve high speed operation while maintaining low CMOS power dissipation.
Features
s 1.65V to 3.6V VCC supply operation s 3.6V tolerant inputs and outputs s 26 series resistors in outputs s tPD 3.9 ns max for 3.0V to 3.6V VCC 4.6 ns max for 2.3V to 2.7V VCC 8.2 ns max for 1.65V to 1.95V VCC s Power-off high impedance inputs and outputs s Supports live insertion and withdrawal (Note 1) s Uses patented noise/EMI reduction circuitry s Latchup conforms to JEDEC JED78 s ESD performance: Human body model > 2000V Machine model > 200V
Note 1: To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pull-up resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver.
Ordering Code:
Order Number 74ALVC162827T Package Number MTD56 Package Description 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix "X" to the ordering code.
Logic Symbol
Pin Descriptions
Pin Names OEn I0-I19 O0-O19 Description Output Enable Input (Active LOW) Inputs Outputs
(c) 2001 Fairchild Semiconductor Corporation
DS500698
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74ALVC162827
Connection Diagram
Truth Tables
Inputs OE1 L L H X OE2 L L X H Inputs OE3 L L H X OE4 L L X H I0-I9 L H X X I0-I9 L H X X Outputs O0-O9 L H Z Z Outputs O10-O19 L H Z Z
H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial (HIGH or LOW, inputs may not float) Z = High Impedance
Functional Description
The 74ALVC162827 contains twenty non-inverting buffers with 3-STATE outputs. The device is byte controlled with each byte functioning identically, but independent of each other. The control pins may be shorted together to obtain full 20-bit operation. The 3-STATE outputs are controlled by Output Enable (OEn) inputs. When OE1, and OE2 are LOW, O0-O10 are in the 2-state mode. When either OE1 or OE2 are HIGH, the standard outputs are in the high impedance mode but this does not interfere with entering new data into the inputs. The same applies for byte two with OE3 and OE4.
Logic Diagrams
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74ALVC162827
Absolute Maximum Ratings(Note 2)
Supply Voltage (VCC) DC Input Voltage (VI) Output Voltage (VO) (Note 3) DC Input Diode Current (IIK) VI < 0V DC Output Diode Current (IOK) VO < 0V DC Output Source/Sink Current (IOH/IOL) DC VCC or GND Current per Supply Pin (ICC or GND) Storage Temperature Range (TSTG)
-0.5V to +4.6V -0.5V to 4.6V -0.5V to VCC +0.5V -50 mA -50 mA 50 mA 100 mA -65C to +150C
Recommended Operating Conditions (Note 4)
Power Supply Operating Input Voltage Output Voltage (VO) Free Air Operating Temperature (TA) Minimum Input Edge Rate (t/V) VIN = 0.8V to 2.0V, VCC = 3.0V 10 ns/V
Note 2: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the Absolute Maximum Ratings. The "Recommended Operating Conditions" table will define the conditions for actual device operation. Note 3: IO Absolute Maximum Rating must be observed. Note 4: Floating or unused control inputs must be held HIGH or LOW.
1.65V to 3.6V 0V to VCC 0V to VCC
-40C to +85C
DC Electrical Characteristics
Symbol VIH Parameter HIGH Level Input Voltage Conditions VCC (V) 1.65 - 1.95 2.3 - 2.7 2.7 - 3.6 VIL LOW Level Input Voltage 1.65 - 1.95 2.3 - 2.7 2.7 - 3.6 VOH HIGH Level Output Voltage IOH = -100 A IOH = -2 mA IOH = -4 mA IOH = -6 mA IOH = -8 mA IOH = -12 mA VOL LOW Level Output Voltage IOL = 100 A IOL = 2 mA IOL = 4 mA IOL = 6 mA IOL = 8 mA IOL = 12 mA II IOZ ICC ICC Input Leakage Current 3-STATE Output Leakage Quiescent Supply Current Increase in ICC per Input 0 VI 3.6V 0 VO 3.6V VI = V CC or GND, IO = 0 VIH = VCC - 0.6V 1.65 - 3.6 1.65 2.3 2.3 3 2.7 3.0 1.65 - 3.6 1.65 2.3 2.3 3 2.7 3 3.6 3.6 3.6 3 - 3.6 VCC - 0.2 1.2 1.9 1.7 2.4 2 2 0.2 0.45 0.4 0.55 0.55 0.6 0.8 5.0 10 40 750 A A A A V V Min 0.65 x VCC 1.7 2.0 0.35 x VCC 0.7 0.8 V V Max Units
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74ALVC162827
AC Electrical Characteristics
TA = -40C to +85C, RL = 500 Symbol Parameter CL = 50 pF VCC = 3.3V 0.3V Min tPHL, tPL tPZL, tPZH tPLZ, tPHZ Propagation Delay Bus to Bus Output Enable Time Output Disable Time 1.3 1.3 1.3 Max 3.9 4.8 4.8 VCC = 2.7V Min 1.5 1.5 1.5 Max 4.6 5.4 5.4 CL = 30 pF VCC = 2.5V 0.2V Min 1.0 1.0 1.0 Max 4.1 5.9 4.9 VCC = 1.8V 0.15V Min 1.5 1.5 1.5 Max 8.2 9.8 8.8 ns ns ns Units
Capacitance
Symbol CIN COUT CPD Input Capacitance Output Capacitance Power Dissipation Capacitance Parameter Conditions VI = 0V or VCC VI = 0V or VCC Outputs Enabled f = 10 MHz, CL = 50 pF TA = +25C VCC 3.3 3.3 3.3 2.5 Typical 6 7 20 20 Units pF pF pF
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74ALVC162827
AC Loading and Waveforms
TABLE 1. Values for Figure 1 TEST tPLH, tPHL tPZL, tPLZ tPZH, tPHZ SWITCH Open VL GND
FIGURE 1. AC Test Circuit TABLE 2. Variable Matrix (Input Characteristics: f = 1MHz; tr = tf = 2ns; Z0 =50 Symbol Vmi Vmo VX VY VL VCC 3.3V 0.3V 1.5V 1.5V VOL + 0.3V VOH - 0.3V 6V 2.7V 1.5V 1.5V VOL + 0.3V VOH - 0.3V 6V 2.5V 0.2V VCC/2 VCC/2 VOL + 0.15V VOH - 0.15V VCC*2 1.8V 0.15V VCC/2 VCC/2 VOL + 0.15V VOH - 0.15V VCC*2
FIGURE 2. Waveform for Inverting and Non-Inverting Functions
FIGURE 3. 3-STATE Output High Enable and Disable Times for Low Voltage Logic
FIGURE 4. 3-STATE Output Low Enable and Disable Times for Low Voltage Logic
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74ALVC162827 Low Voltage 20-Bit Buffer/Line Driver with 3.6V Tolerant Inputs and Outputs and 26 Series Resistors in the Outputs
Physical Dimensions inches (millimeters) unless otherwise noted
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Package Number MTD56
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 6 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com

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